1. Technical Field
The present invention relates generally to communication links including, but not limited to, serial interfaces for integrated circuits.
2. Description of the Background Art
High-speed communication links using serial interface protocols are used to communicate data between devices in a system. Most multiple gigabit per second (Gbps) high-speed input/output (HSIO) links are serial where the bit clock is embedded in the transmitting data bit stream and gets recovered at the receiver through a clock and data recovery (CDR) circuit. Examples of industry-standard protocols for HSIO include those related to PCI Express® (Peripheral Component Interconnect Express), XAUI (X Attachment Unit Interface), sRIO (serial Rapid IO), and many others.
For copper-based serial links, the frequency dependent loss may become severe and various equalizations (EQs) may need to be invoked to compensate the high-frequency signal loss. Commonly used equalization techniques may include linear equalization and non-linear adaptive equalization. Examples of linear equalization include finite impulse response (FIR) and feed forward equalization (FFE). Examples of nonlinear adaptive equalization include decision feedback equalization (DFE) and infinite impulse response (IIR).
For an HSIO link, the dominant contributors to overall system BER are jitter and noise from all the subsystems of the link. In order to ensure interoperability, many high-speed link standards specify the signal waveform, eye diagram, jitter, and noise properties at the output of the transmitter and also specify the inputs of the receiver. In order to be certain that a device will work well when it is integrated and used in a system, a device may be simulated to verify that it passes the specification requirements.
The circuit simulator HSPICE may be used to simulate the operation of integrated circuits. The time to simulate an integrated circuit with HSPICE, however, may be very long, such that the simulation becomes somewhat impractical. HSPICE may take several hours or days to simulate transceiver circuit blocks with a data pattern which is of moderate length. For example, HSPICE may take many days to simulate transceiver circuit with a pseudorandom binary sequence (PRBS) of length (215−1) bits (which may be referred to as PRBS-15). A PRBS-15 data pattern is tens of thousands of bits long.
In order to reduce simulation time with increased coverage of the transceiver building blocks, a behavior-level simulator may be used. Behavior-level simulators include, for example, a pre-emphasis and equalization link estimator (PELE), and other simulators. Such a behavior-level simulator takes minutes to hours to simulate the performance of a HSIO link [including, for example, transceiver circuits and the channel medium (e.g., PCB trace, connectors, vias) in between] so as to determine a simulated eye diagram and BER for a moderate length data pattern.
While HSPICE and behavior-level simulation may be used for transceiver circuit simulation with moderate-length data patterns, it is not feasible to use HSPICE and behavior-level simulation for substantially longer data patterns, such as a PRBS31 data pattern, which is a PRBS of length (231-1) bits. A PRBS-31 data pattern is over a billion bits long and so would take a very long time to simulate. In addition, simulating a very long data pattern, such as PRBS-31, may be beyond the limited memory capabilities of the computer apparatus performing the simulation.
Another challenge in the simulation of high-speed links is how to obtain channel information. For example, channel S-parameters are usually measured by vector network analyzer (VNA), or simulated by an electromagnetic (EM) field solver. However, once network systems are deployed, the actual channels cannot be measured by VNA. Deployed channel information, such as an impulse or step response, may instead be measured with an embedded instrument such as on-die instrument (ODI). If the channel information is given, then behavior-level simulation, such as PELE, may be useful to fine-tune adaptively obtained channel equalizer settings, such as, for example, TX pre-emphasis, RX continuous-time linear equalization (CTLE) and DFE.